Chinese chipmaking methodology gains support amid US sanctions
L'essentiel
- Empyrean Technology, a Chinese EDA provider, has backed a new chipmaking method using "true-3D" stacking, compatible with Huawei's LogicFolding architecture.
- This approach, presented as an alternative to Moore's Law, aims to bypass US sanctions on advanced lithography equipment by compressing signal travel time instead of shrinking transistors.
Résumé généré par IA
Empyrean Technology, a major Chinese electronic design automation (EDA) provider, became the latest supporter of the new chipmaking methodology.
The announcement followed a claimed breakthrough by researchers at Peking University, who unveiled a prototype EDA tool using a “true-3D” approach, said to be compatible with Huawei’s LogicFolding architecture. That milestone came just one day after Huawei introduced its Tau Scaling framework late last month.
Presented as an alternative to Moore’s Law, the Tau Scaling Law shifts the focus of chip development from shrinking transistors to compressing signal travel time across a system.
By stacking flat circuits vertically into 3D structures through “LogicFolding”, the approach aims to match the transistor density and performance of leading-edge chips without relying on advanced Western lithography equipment restricted by US sanctions.
