Nanya (2408) Xiaojinji Patch Technology (7947) will be listed on the IPO on the 16th of this month at a reference price of 740 yuan per share. In recent years, with the rapid expansion of the scale of AI models, the demand for high-bandwidth, low-latency, and low-power memory has been boosted. Patch Technology uses 3D stacking and Near Memory architecture has entered the AI memory upgrade business opportunity, and revenue and profits have grown simultaneously. Li Xiaowen, general manager of Patch Technology, said that customized design service (NRE) revenue accounts for about 40% of the company's revenue. As existing projects gradually advance, the proportion of subsequent Royalty (royalty) and Turnkey (mass production) revenue is expected to further increase. There are currently multiple customer projects in progress simultaneously. According to the current development progress, mass production results are expected to begin to appear from 2027.
With the rapid development of AI and the continuous improvement of computing power, the demand for memory bandwidth is more urgent than before, and has become an important key to the performance of AI computing. Patchtech said that with nearly 20 years of memory IC design experience, it has actively developed AI high-bandwidth memory circuit technology, 3D wafer stacking (Wafer-on-Wafer, WoW) and Near Memory architecture provides AI memory solutions with high bandwidth, low latency and low power consumption. Based on core technology and design capabilities, it develops diversified businesses such as memory IP licensing, customized IC design services, mass production services and standardized DRAM products, and gradually builds a diversified and high value-added operating model.
Patchtech said that the company has long invested in the development of high-performance memory architecture and extended its core technology to 3D integration and co-design of memory and logic chips, which can effectively increase bandwidth, reduce latency, and reduce the power consumption and heat dissipation burden caused by data movement. It helps break through "The Memory Wall" and is more in line with the needs of AI inference, high-performance computing (HPC) and Edge AI for high-efficiency computing. As the scale of AI models continues to expand, data transmission efficiency, power consumption control and advanced packaging integration capabilities have become the key to the next stage of AI chip competition. Patch Technology has entered the field of high-bandwidth memory technology and has clear growth momentum.
In terms of industrial cooperation, Patchtech has established a strategic partnership with Nanya, and uses advanced processes and 3D stacking technology from major wafer foundries with customers to jointly create a complete AI memory supply chain. The company is also currently promoting cooperation projects with a number of international semiconductor companies and North American customers. Some projects have entered the design, development and verification stages, and are expected to be gradually introduced into mass production along with the customer's product schedule, further expanding business development such as IP licensing, NRE and Turnkey mass production services.
In terms of operating performance, thanks to the continued expansion of AI applications, the recovery of the memory market and the smooth advancement of customer projects, Patch Technology has strong growth momentum. In 2025, consolidated revenue will reach 823 million yuan, an annual increase of 97%, with net profit after tax of 205 million yuan, earnings per share of 3.76 yuan, and gross profit margin of 46%. The benefits of product portfolio and high value-added services are gradually fermented. In the first half of 2026, consolidated revenue reached 1.088 billion yuan, a significant increase of 248% compared with the same period last year. Net profit after tax was 564 million yuan, and earnings per share were 9.35 yuan. Revenue and profits rose simultaneously.
Patch Branch pointed out that its current revenue mainly comes from memory IC products, customized IC design technology services (NRE) and other income. In the future, it will continue to increase the proportion of IP licensing and high value-added business, optimize the revenue structure and improve profitability. Looking forward to the future, Patchtech will continue to deepen core technologies such as 3D wafer stacking, high-bandwidth low-latency memory and Near Memory architecture, and work with international customers and industry partners to jointly promote AI memory technology innovation. Patchtech plans to register on September 16th. By entering the capital market to expand R&D energy and accelerate international market layout, it will move towards the goal of becoming a global AI memory IP leader.
